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vertical driver for ccd cameras data sheet ADDI9023 rev. 0 information furnished by analog devices is believed to be a ccurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is gr anted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2012 analog devices, inc. all rights reserved. features 12- channel vertical driver 8 three - level drivers 4 two - level drivers substrate clock driver input logic supports a 1.6 v to 3.6 v range output drivers support a ? 9.5 v to +15.5 v range 6 mm 6 mm csp_bga package with 0.65 mm pitch applications di gital s till c ameras industrial cameras surveillance cameras medical imaging general description the ADDI9023 is a 12 - c hannel vertical driver for charge - coupled device ( ccd ) imaging applications. it includes eight three - level drivers and four two - level drivers. the input configuration can support up to nine individual vertical timing phases and eight shift gate signals. a separate substrate clock channel (subck) is also included. typical load drive capability for each channel is 3 n f. the ADDI9023 is specified over an operating temperature range of ? 25c to +85c. functional block dia gram v8 xv8 three-level outputs two-level outputs v6 v7 xv7 xsg1 xv1 xsg2 xsg3 xv2 xsg4 xv3 xsg6 xv4 xsg7 xv6 xsg8 xv9 xsubck v9 subck v1a + + v1b v2a v2b v3a v3b v4 v5 xsg5 + + + + vll ADDI9023 + + xv5 10693-004 vdd vh vm vl figure 1.
ADDI9023 data sheet rev. 0 | page 2 of 12 t able of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 output driver specifications ...................................................... 4 absolute maximum ratings ............................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configuration and function descriptions ..............................6 input/output logic states ................................................................8 applications information .............................................................. 10 power - up sequence ................................................................... 10 power - down seque nce .............................................................. 10 circuit layout information ....................................................... 11 outline dimensions ....................................................................... 12 order ing guide .......................................................................... 12 revision history 4/12 revision 0: initial version
data sheet ADDI9023 rev. 0 | page 3 of 12 specifications table 1 . parameter test conditions/comments min typ max unit temperature range operating ?25 +85 c storag e ?65 +150 c v - driver power supply voltages vdd input l ogic s upply 1.6 3.0 3.6 v vh v - d river h igh s upply 11.0 15.0 15.5 v vl v - d river l ow s upply ?9.5 ?7.5 ?5.5 v vm v - d river mids upply ?1.5 0.0 +1.5 v vll subck v - d river l ow s upply ?9.5 ?7.5 ? 5.5 v vh to vl, vll maximum voltage from vh to vl, vll 24 v dc power supply currents vh = +15 v, vm = 0 v, vl = vll = ?7.5 v i vdd xvx = xsgx = 0 v 0.5 ma xvx = xsgx = vdd 0.5 ma i vh xvx = xsgx = 0 v 0.4 ma xvx = xsgx = vdd 3.3 ma i vl xvx = xsgx = 0 v 2.1 ma xvx = xsgx = vdd 0.1 ma i vm xvx = xsgx = 0 v 0.3 ma xvx = xsgx = vdd 0.2 ma i vll xsubck = 0 v 0.3 ma xsubck = vdd 0.1 ma digital inputs vdd = 1.6 v to 3.6 v high level input voltage vdd ? 0.6 v low lev el input voltage 0.6 v high level input current 10 50 a low level input current 10 50 a input capacitance 10 pf
ADDI9023 data sheet rev. 0 | page 4 of 12 output driver specif ications vh = 15 v , vm = 0 v , vl, vll = ? 7.5 v , t a = 25c. table 2 . parameter symb ol test conditions/comments min typ max unit v1a to v5 de lay time, vl to vm and vm to v l t plm , t pm l 37 ns de lay time, vm to v h and vh to vm t pm h , t phm 43 ns rise time, vl to vm t rlm load circuit: 20 + 3 nf to gnd 1 1 0 ns rise time, vm t o vh t rmh load circuit: 20 + 3 nf to gnd 240 ns fall time, vm to vl t fml load circuit: 20 + 3 nf to gnd 180 ns fall time, vh to vm t fhm load circuit: 20 + 3 nf to gnd 1 30 ns output currents v1a to v5 = ?7.25 v 14 ma v1a to v5 = ?0.25 v ?23 ma v1a to v5 = +0.25 v 23 ma v1a to v5 = +14.75 v ?10 ma on resistance r on vh 23 35 vm 11 20 vl 17 25 v6 to v9 delay time, vl to vm and vm to vl t plm , t pml 37 ns rise time, vl to vm t rlm load ci rcuit: 20 + 3 nf to gnd 1 1 0 ns fall time, vm to vl t fml load circuit: 20 + 3 nf to gnd 1 8 0 ns output currents v6 to v 9 = ?7.25 v 1 4 ma v6 to v 9 = ? 0 .25 v ?2 3 ma on resistance r on vm 11 20 vl 17 25 subck output delay time, vll to vh t plh 47 ns delay time, vh to vll t phl 47 ns rise time, vll to vh t rlh load circuit: 1 nf to gnd 45 ns fall time, vh to vll t fhl load circuit: 1 nf to gnd 45 ns output currents subck = ?7.25 v 23 ma s ubck = +14.75 v ?22 ma vll on resistance r on 10 17 v -driver input t rlm , t rmh , t rlh 50% 10% 90% t plm , t pmh , t plh v -driver output 10% 50% 90% t fml , t fhm , t fh l t pml , t phm , t ph l 10693-002 figure 2 . definition of v - driver timing specifications
data sheet ADDI9023 rev. 0 | page 5 of 12 absolute maximum rat ings table 3 . parameter rating vdd to vss ?0.3 v to +3.9 v vh to v l, vll ?0.3 v to +25.0 v vh to vss ?0.3 v to +17.0 v vl to vss ?17.0 v to +0.3 v vm to vss ?6.0 v to +3.0 v vmm to vss ?6.0 v to +3.0 v vll to vss ?17.0 v to +0.3 v v1a to v9 to vss vl ? 0.3 v to vh + 0.3 v vdren to vss ?0.3 v to vdd + 0.3 v junc tion temperature 150c lead temperature (soldering, 10 sec) 350c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 4 . thermal resistance package type ja unit 40- lead csp_bga 46 c/w esd caution
ADDI9023 data sheet rev. 0 | page 6 of 12 pin configur ation and function d escriptions 1 2 3 4 5 6 7 1 2 3 4 5 6 7 a b c d e f g a b c d e f g ADDI9023 top view (not to scale) vdd subck xv9 xv4 xv8 xv1 xv2 xv5 xv3 xv7 vss vss vdren xsubck vm vmm vl vll vh v1a v6 v5 v4 v3b v3a v2b v9 v2a v8 v1b v7 xsg1 xsg8 xsg7 xsg6 xsg5 xsg4 xsg3 xsg2 xv6 10693-003 figure 3. pin configuration table 5 . pin function descriptions pin no. mnemonic type 1 description a1 vm p v - driver midsupply. a2 vl p v - driver low supply. a3 vh p v - dri ver high supply. a4 vdren di v -d river enable. active h igh. a5 xsg8 di vertical input . a6 xsg5 di vertical input . a7 xsg6 di vertical input . b1 v8 vo2 ccd vertical transfer clock. b2 v7 vo2 ccd vertical transfer clock. b3 v9 vo2 ccd vertical transfer clock. b4 xsg7 di vertical input . b5 xsg2 di vertical input . b6 xsg3 di vertical input . b7 xsg4 di vertical input . c1 v6 vo2 ccd vertical transfer clock. c2 v5 vo3 ccd vertical transfer clock ( xv5 + xsg8 ). c6 xv8 di vertical input . c7 xsg1 di vert ical input . d1 v4 vo3 ccd vertical transfer clock ( xv4 + xsg7 ). d2 v3b vo3 ccd vertical transfer clock ( xv3 + xsg6 ). d6 xv7 di vertical input . d7 xv9 di vertical input . e1 v2b vo3 ccd vertical transfer clock ( xv2 + xsg4 ). e2 v3a vo3 ccd vertical tran sfer clock ( xv3 + xsg5 ). e6 xv5 di vertical input . e7 xv6 di vertical input .
data sheet ADDI9023 rev. 0 | page 7 of 12 pin no. mnemonic type 1 description f1 v1b vo3 ccd vertical transfer clock ( xv1 + xsg2 ). f2 v2a vo3 ccd vertical transfer clock ( xv2 + xsg3 ). f3 xsubck di xsubck input to subck buffer. f4 xv1 di vertical input . f5 xv2 di vertical input . f6 xv3 di vertical input . f7 xv4 di vertical input . g1 v1a vo3 ccd vertical transfer clock ( xv1 + xsg1 ). g2 subck vo2 ccd substrate clock output. g3 vmm p subck output driver ground. g4 vll p v - driver low supply for subck output. g5 vdd p digital logic supply. g6 vss p digital logic ground. g7 vss p digital logic ground. 1 di = digital input; p = power; vo2 = vertical driver out put , two - level ; vo3 = vertical driver outp ut , three - level.
ADDI9023 data sheet rev. 0 | page 8 of 12 in put/output logic sta tes table 6 . v1a output polarity vertical driver input v1a output xv1 xsg1 l l vh l h vm h l vl h h vl table 7 . v1b output polarity vertical driver input v1b output xv1 xsg2 l l vh l h vm h l vl h h vl table 8 . v2a output polarity vertical driver input v2a output xv2 xsg3 l l vh l h vm h l vl h h vl table 9 . v2b output polarity vertical driver input v2b output xv2 xsg4 l l vh l h vm h l vl h h vl table 1 0 . v3a output polarity vertical driver input v3a output xv3 xsg5 l l vh l h vm h l vl h h vl table 11 . v3b output polarity vertical driver input v3b output xv3 xsg6 l l vh l h vm h l vl h h vl table 12 . v4 output polarity vertical driver input v4 output xv4 x sg7 l l vh l h vm h l vl h h vl table 13 . v5 output polarity vertical driver input v5 output xv5 xsg 8 l l vh l h vm h l vl h h vl table 14 . v6 to v9 output polarity vertical driver input v 6, v 7, v8, or v9 output xv 6, xv7, xv8, or xv9 l vm h vl table 15 . subck output polarity vertical driver input subck output xsubck l vh h vll
data sheet ADDI9023 rev. 0 | page 9 of 12 xv1, xv2, xv3, xv4, xv5 v1a, v1b, v2a, v2b, v3a, v3b, v4, v5 xsg1, xsg2, xsg3, xsg4, xsg5, xsg6, xsg7, xsg8 vh vm vl 10693-005 figure 4. three - level v - driver output polarities xv6, xv7, xv8, xv9 v6, v7, v8, v9 vl vm 10693-006 figure 5. two - level v - driver output polarities subck xsubck vh vll 10693-007 figure 6 . subck output polarity
ADDI9023 data sheet rev. 0 | page 10 of 12 applications informa tion power - up sequence when the ADDI9023 is powered up, the following sequence is recommended (refer to figure 7 for each step). note that vh is powered on before vl but , depending on ccd restrictions , vh and vl can also be powered on simultaneously. 1. turn on the vdd power supply, either 1.8 v or 3.3 v. after vdd settle s , the logic inputs from the timing generator (xv, xsg, xsubck) can become active. keep vdren low during this time. 2. turn on the vh power supply, typically +12 v to +15 v. 3. turn on the vl/vll power supply, typically ? 6 v to ? 9 v. 4. take the vdren pin high to enable the v - driver outputs. vdren must remain high throughout normal vertical timing operation. power - down sequence when the ADDI9023 is powered down , reverse the proced ure shown in figure 7 . 1. take the vdren pin low to disable the v - driver outputs. 2. turn off the vl/vll and vh power supplies. 3. turn off the vdd power supply. 0v vh supply vl, vll supply 1 2 0v vm vh vl/vl l (subck on l y) xv , xsg, xsubck (input) vm v-driver outputs active when vdren is high vdd v1a t o v9 (output) vdren power supplies 0v 0v vdd 4 vdd 3 don?t care 10693-008 figure 7 . recommended power- up sequence
data sheet ADDI9023 rev. 0 | page 11 of 12 circuit layout infor mation the recommended circuit configuration is shown in figure 8 . each supply pin should have a high quality 0.1 f capacitor connected to ground. the vh and vl supplies should have an additional bypass capacitor, such as a 1.0 f to 22 f capacitor, depending on ccd and performance requirements. connect t he ground pins (vss, vm, and vmm) to a common ground plane. ADDI9023 (not to scale) vss vm vmm xv8 xv7 xsg1 xv1 xsg2 xsg3 xv2 xsg4 xv3 xsg6 xv4 xsg7 xv6 xsg8 xv9 xsubck xsg5 xv5 18 c6 d6 c7 f4 b5 b6 f5 b7 f6 a7 f7 b4 e7 a5 d7 f3 a6 e6 v1a v1b v2a v2b v3a v3b v5 v6 v8 v7 subck v4 v9 13 g1 f1 f2 e1 e2 d2 c2 c1 b1 b2 g2 d1 b3 g3 a1 g6 g7 vss g5 a3 g4 a2 25v 10v 0.1f +3.3v supply vh supply vl supply 1.0f 25v 4.7f 0.1f 0.1f 10v + v-driver outputs (to ccd) logic inputs (from timing generator) a4 vdren v-driver output enable active high (from general-purpose output) vll vdd vh vl 10693-009 figure 8 . typical circuit con figuration
ADDI9023 data sheet rev. 0 | page 12 of 12 outline dimensions 04-30-2012- a 3.90 bsc sq 0.30 nom 0.25 min 0.45 0.40 0.35 * 1.04 0.96 0.81 * 0.76 0.66 0.56 6.10 6.00 sq 5.90 coplanarit y 0.10 a b c d e f g 7 6 3 2 1 5 4 ball diameter 0.65 bsc 1.05 ref de t ai l a a1 ball corner a1 ball corner detail a bottom view top view seating plane * compliant to jedec standards mo-225 with the exception of package height and thickness. figure 9 . 40 - ball chip scale package ball grid array [csp_bga] bc - 40 - 1 dimensions shown in millimeters ordering guide model 1 tempe rature range package description package option ADDI9023bbcz ? 25c to +85c 40- lead csp_bga bc -40-1 ADDI9023bbcz rl ? 25c to +85c 40- lead csp_bga bc -40-1 1 z = rohs compliant part. ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of th eir respective owners. d10693 - 0 - 4/12(0)

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